New PDF release: Analog Circuit Design: Low-Power Low-Voltage, Integrated
By Eric A. Vittoz (auth.), Rudy J. van de Plassche, Willy M. C. Sansen, Johan H. Huijsing (eds.)
The consciousness of sign sampling and quantization at excessive pattern premiums with low energy dissipation is a vital aim in lots of functions, includ ing transportable video units resembling camcorders, own conversation units corresponding to instant LAN transceivers, within the learn channels of magnetic garage units utilizing electronic info detection, and so forth. This paper describes structure and circuit ways for the layout of high-speed, low-power pipeline analog-to-digital converters in CMOS. the following the time period excessive velocity is taken to indicate sampling charges above 1 Mhz. within the first part the dif ferent conversion options acceptable during this diversity of pattern charges is dis stubborn. Following that the actual difficulties linked to strength minimization in video-rate pipeline ADCs is mentioned. those contain optimi zation of capacitor sizes, layout of low-voltage transmission gates, and opti mization of switched capacitor achieve blocks and operational amplifiers for minimal energy dissipation. to illustrate of the applying of those tech niques, the layout of a power-optimized lO-bit pipeline relief converter (ADC) that achieves =1. sixty seven mW in step with MS/s of sampling fee from 1 MS/s to twenty MS/s is defined. 2. innovations for CMOS Video-Rate reduction Conversion Analog-to-digital conversion options might be categorised in lots of methods. One handy technique of evaluating strategies is to check the variety of "analog clock cycles" required to provide one powerful output pattern of the sign being quantized.
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Additional info for Analog Circuit Design: Low-Power Low-Voltage, Integrated Filters and Smart Power
Keep the sum of the base-emitter voltages of the output transistors constant. In order to obtain a quiescent current in the output transistors which is inde- 32 Vee Vee - V + s "2 lout Irl Vin V + s "2 VEE Fig. 19a. Conventi01UlI Class-AB output stage. Fig. 19b. Rail-to-rail ClassAB output stage. pendent of the supply voltage, the voltage Vs should be equal to the supply voltage. A similar discussion can be held for CMOS output stages. Fig. 20 shows a first example of the principle depicted in Fig.
12]. The amplifier consists of an input stage, Q3rQ32. an intermediate stage, Q2J-Q22' and an output stage. Q/. Each stage has a dominant pole at its output. The magnitude plot is shown in Fig. 29. ,. ,. I I i'i C R', _... ,. I ~----~~~--~-----L----~----~--~~~VEE Fig. 28. Three-stage amplifier with nested Miller compensation. t Voltage gain (dB) frequency (Hz) - Fig. 29. The open-loop gain o/the three-stage amplifier with nested Miller compensation. fier with two dominant poles, /} and h. The capacitor CM } closes the first Miller loop which splits h and h to h' and h', respectively.
38. 9 V. r - - - - - r - - - __ vpp ~--~-~---~-~--VNN Fig. 38. BiCMOS multipath driven output stage VII. Conclusions The maximum dynamic range of low-voltage low-power amplifiers is squeezed between the low supply-voltages and the larger thennal noise voltages caused by the lower supply currents. To obtain the maximum 46 dynamic range the input and output stages should be able to handle rail-torail signal voltages. Bipolar and CMOS rail-to-rail input stages with constant-gm have been presented.